Design of 120∶1 frequency divider for a 12.6 GHz phase-locked loop

Author

Duong, H.T. ; Tran, N. ; Huynh, A.T. ; Le, Hung V. ; Skafidas, E.

Author_Institution

Dept. of Electr. & Electron. Eng., Univ. of Melbourne, Melbourne, VIC, Australia

fYear

2014

fDate

26-27 June 2014

Firstpage

33

Lastpage

34

Abstract

A 120:1 frequency divider in 65-nm CMOS process is proposed. As a critical part of a 12.6 GHz PLL, the divider circuit divides the 12.6 GHz signal by a factor of 120 to achieve a 105 MHz reference signal. The design includes an 8:1 analog common mode logic (CML) divider followed by a 15:1 digital frequency divider. The measurement results show that it achieves a low phase noise of -109 dBc/Hz at 1 MHz offset, and a wide locking range from 8.3 GHz to 13.9 GHz. The size of the fabricated divider is 0.3 × 0.1 mm².

Keywords

CMOS analogue integrated circuits; frequency dividers; microwave integrated circuits; phase locked loops; CML divider; CMOS process; PLL; analog common mode logic divider; digital frequency divider; divider circuit; frequency 8.3 GHz to 13.9 GHz; frequency divider; phase-locked loop; size 65 nm; CMOS integrated circuits; Frequency conversion; Frequency measurement; Noise measurement; Phase locked loops; Phase measurement; Phase noise; CML; CMOS; PLL; frequency divider;

fLanguage

English

Publisher

ieee

Conference_Titel

Microwave Symposium (AMS), 2014 1st Australian

Conference_Location

Melbourne, VIC

Type

conf

DOI

10.1109/AUSMS.2014.7017352

Filename

7017352