Characterisation and modelling of planar on-chip integrated Peltier elements for highly localised thermal stabilisation and cooling

On-chip integrated Peltier elements are ideally suited for highly localised on-chip thermal stabilisation. The nonidealities are analysed with respect to the impact on device performance and are used to derive the proper performance optimisation criteria. Furthermore, an FEA model is presented which incorporates the Peltier effect itself, as well as the nonidealities. As thermoelectric material, polySiGe is used, because of its good balance between thermoelectric performance and fabrication compatibility. Both the experimental validation of the thermophysical properties, as well as the performance measurements on the first generation integrated Peltier elements are presented and discussed.