DocumentCode
2360344
Title
SCAN/BIST techniques for decreasing test storage and their implications to test pattern generation
Author
Bevacqua, R. ; Guerrazzi, L. ; Fummi, F.
Author_Institution
Dipartimento di Elettronica e Inf., Politecnico di Milano, Italy
fYear
1996
fDate
2-5 Sep 1996
Firstpage
351
Lastpage
358
Abstract
Test pattern storage is an important problem affecting all Design for Testability (DfT) techniques based on scan-path. Built-In Self Test (BIST) methodologies are used in conjunction to scan-path techniques for reducing the amount of test patterns that must be stored. This paper analyzes two SCAN/BIST approaches and identifies conditions which guarantee that such techniques require shorter test sequences in relation to a simple scan method. Such conditions concern the ability of sequential test pattern generators (TPGs) to concatenate test sequences, but, unfortunately, standard sequential TPGs do not show sufficient capabilities in this task. This, the paper presents an innovative concatenation strategy for test sequences based on implicit techniques. Preliminary results and a case-study show that the use of the presented SCAN/BIST approaches, with the proposed test generation strategy, generates a test methodology that sensibly reduce the amount of test patterns which must be stored
Keywords
built-in self test; design for testability; logic testing; BIST; Built-In Self Test; Design for Testability; SCAN; scan-path techniques; test pattern generation; test sequences; test storage; Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Combinational circuits; Costs; Design for testability; Sequential analysis; Sequential circuits; Test pattern generators;
fLanguage
English
Publisher
ieee
Conference_Titel
EUROMICRO 96. Beyond 2000: Hardware and Software Design Strategies., Proceedings of the 22nd EUROMICRO Conference
Conference_Location
Prague
ISSN
1089-6503
Print_ISBN
0-8186-7487-3
Type
conf
DOI
10.1109/EURMIC.1996.546458
Filename
546458
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