A sensitivity study on BGA package parameters that affect pin capacitance

To reduce the degradation of signal integrity in substrate-based, chip-on-board (COB), ball grid array (BGA) packages caused by excessive trace capacitance, a sensitivity study on package trace capacitance is presented. A test vehicle was designed and simulated for the sensitivity study using Ansoft high frequency structure simulator (HFSS). Nine potential package parameters that can affect trace capacitance are varied from their nominal values, and the variation in trace capacitance is analyzed. These nine parameters are narrowed down to four parameters that result in the highest impact to trace capacitance and simulated in a typical COB BGA design using Ansoft turbo package analyzer (TPA). The impact of the parameters´ variations on pin capacitance is compared. Measured results show that the memory device in the package contributes to pin capacitance significantly and reduces impact by more than 50%. Comparing the measures implemented in the improved package design show an average pin capacitance reduction of 20%. With a memory die in the package, percentage reduction is diminished to 7.7%.