Reliability Analysis for On-chip Networks under RC Interconnect Delay Variation

Future integrated circuits are characterized by their high defect rates thereby necessitating certain degree of redundancy. In a typical network-on-chip (NoC), multiple paths exist between a source and a sink to provide the required level of fault tolerance. Consequently, a manufacturing fault on a single interconnect does not necessarily render the resulting integrated circuit useless. In this paper we quantify the fault tolerance offered by an NoC. Specifically, we (1) provide a model for determining the probability that an NoC link fails due to manufacturing variation, and (2) measure the impact of link failure on the number of cycles taken by the NoC to implement communication