A Novel 1GSPS Low Offset Comparator for High Speed ADC

In high speed ADC, comparator influence the overall performance of ADC directly. This paper describes an ultra high speed and low offset preamplifier-latch comparator. The comparator use two negative resistors parallel with positive resistors as load resistors of preamplifier to improve its gain so as to reduce offset voltage. Meanwhile, the comparator uses a novel method to reduce the recovery time of regenerative stage by add a pre-set quiescent current. Based on TSMC 0.18 mum CMOS process model, simulated results show the comparator can work under ultra high speed clock frequency 1 GHz. The comparator has a low offset voltage (0.9 mV), a short fall delay time (60 ps) and rise delay time (50 ps). With 1 V swing, it is suitable for 10 bit 1GSPS high speed ADC.