DocumentCode
2363130
Title
A 3-D re-configurable image processing element
Author
O´Donnell, L. ; Williams, G.L. ; Lacey, A.J. ; Seed, N.L. ; Thorne, P.R. ; Zawada, A.C. ; Ivey, P A
Author_Institution
Dept. of Electron. & Electr. Eng., Sheffield Univ., UK
fYear
1998
fDate
35838
Firstpage
42370
Lastpage
42376
Abstract
Image processing is generally computationally intensive, and has, traditionally, required high-speed ASICs to produce acceptable real-time speeds. The use of a general-purpose computer (GPC) allows simple verification of an algorithm, but not usually real-time processing. Using an ASIC accelerator with a GPC can yield good performance, however it may have limited functionality due to the pre-defined architecture of the ASIC. Here we present a novel, general-purpose, real-time, re-configurable hardware accelerator with an architecture suitable for rapid image processing. The system, developed as part of an EPSRC-funded project, will also be implemented as a single `device´ using 3D multi-chip module technology
Keywords
image processing; EPSRC-funded project; general-purpose; image processing element; multi-chip module technology; rapid image processing; re-configurable hardware accelerator; real-time;
fLanguage
English
Publisher
iet
Conference_Titel
High Performance Architectures for Real-Time Image Processing (Ref. No. 1998/197), IEE Colloquium on
Conference_Location
London
Type
conf
DOI
10.1049/ic:19980041
Filename
667484
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