Design of a Low Power, Variable-Resolution Flash ADC

Author

Veeramachanen, S. ; Kumar, A.M. ; Tummala, Venkat ; Srinivas, M.B.

Author_Institution

Centre for VLSI & Embedded Syst. Technol., Int. Inst. of Inf. Technol., Hyderabad

fYear

2009

fDate

5-9 Jan. 2009

Firstpage

117

Lastpage

122

Abstract

In this paper, a low power and variable resolution (adaptive) flash ADC is proposed. The ADC enables exponential power reduction while the reduction in resolution is linear. In the proposed design, unused parallel voltage comparators are switched to standby mode leading to consumption of only the leakage power. The ADC, capable of operating at 4-bit, 5-bit, and 6-bit precision, dissipates 6 mW at 4-bit and 12 mW at 6-bit, and operates at a sampling frequency of 1 to 2 GSPS. The ADC has been designed and simulated in standard 65nm CMOS technology using Cadence tools.

Keywords

analogue-digital conversion; comparators (circuits); flash memories; mixed analogue-digital integrated circuits; CMOS technology; Cadence tools; analog-to-digital converter; leakage power consumption; low-power variable-resolution flash ADC; parallel voltage comparators; power 12 mW; power 6 mW; size 65 nm; storage capacity 4 bit; storage capacity 5 bit; storage capacity 6 bit; CMOS technology; Circuits; Energy consumption; Inverters; Photonic band gap; Radio frequency; Regulators; Signal resolution; Very large scale integration; Voltage; Analog-to-digital converter (ADC); CMOS Inverter as a Comparator; Comparator; Flash Type; Peak Detector; Reconfigurability;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Design, 2009 22nd International Conference on

Conference_Location

New Delhi

ISSN

1063-9667

Print_ISBN

978-0-7695-3506-7

Type

conf

DOI

10.1109/VLSI.Design.2009.62

Filename

4749662