• DocumentCode
    2365203
  • Title

    Improving scalability and per-core performance in multi-cores through resource sharing and reconfiguration

  • Author

    Suri, Tameesh ; Aggarwal, Aneesh

  • Author_Institution
    Dept. of Electr. & Comput. Eng., State Univ. of New York at Binghamton, Binghamton, NY
  • fYear
    2009
  • fDate
    5-9 Jan. 2009
  • Firstpage
    145
  • Lastpage
    150
  • Abstract
    Increasing the number of cores in a multi-core processor reduces per-core performance. On the other hand, providing more resources to each core limits the number of cores on a chip. In this paper, we propose a mechanism to improve the per-core performance while maintaining the scalability.In particular, we integrate a Reconfigurable Hardware Unit (RHU) in the resource-constrained cores to improve their performance. The RHU executes the frequently encountered instructions to increase the core´s overall execution bandwidth, thus improving its performance. The RHU has low area overhead, and hence has minimal impact on scalabilityof the number of cores. To further limit the area overhead of this performance improving mechanism, generation of the reconfiguration bits for the RHUs of multiple cores isdelegated to a single core. Our experiments show that the proposed architecture improves the per-core performance by an average of about 23% across a wide range of applications, while incurring a small per-core area overhead.
  • Keywords
    program processors; reconfigurable architectures; multicore processor; per-core performance; reconfigurable hardware unit; resource sharing; scalability; Bandwidth; Hardware; Multicore processing; Performance gain; Resource management; Runtime; Scalability; Very large scale integration; Dynamic Reconfiguration; Heterogeneous Multi-core Design; Instruction Level Parallelism; Multi-core Scalability; Per-core Performance;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Design, 2009 22nd International Conference on
  • Conference_Location
    New Delhi
  • ISSN
    1063-9667
  • Print_ISBN
    978-0-7695-3506-7
  • Type

    conf

  • DOI
    10.1109/VLSI.Design.2009.58
  • Filename
    4749666