TS-LDPC analog decoding based on the Min-Sum algorithm

It has been shown that Min-Sum (MS) algorithms have low complexity in the implementation of analog VLSI decoders compared to the Sum-Product (SP) algorithm. Moreover, Turbo-structured LDPC (TS-LDPC) codes are known to have lower error floor than random LDPC codes. In this paper, Min-Sum and Min-Sum with correction factor algorithms are reviewed and adapted with TS-LDPC codes for future analog VLSI implementation. Simulation results show that the error performance of the Min-Sum algorithm is comparable with the Sum-Product algorithm for the same block length. This means that the lower error floor property of TS-LDPC codes is preserved when MS algorithms are used. Moreover, analog decoder implementation of TS-LDPC codes is studied. To test the suitability of the MS algorithm based TS-LDPC decoder some analog impairments such as mismatch, leakage and noise are considered in the decoding procedure of TS-LDPC codes. In each case, it is shown that the degradation of the error performance of TS-LDPC codes due to analog impairments is negligible. Therefore, it can be concluded that the analog decoder of the TS-LDPC code using MS algorithm is fairly robust against analog imperfections and may be considered in future implementation of analog VLSI decoder.