• DocumentCode
    2366002
  • Title

    A self-aligned latch-free IGBT with sidewall diffused n+ emitter

  • Author

    Yun, Chong-Man ; Kim, Doo-Young ; Lee, Byung-Hoon ; Han, Min-Koo ; Choi, Yearn-Ik

  • Author_Institution
    Dept. of Electr. Eng., Seoul Nat. Univ., South Korea
  • fYear
    1995
  • fDate
    23-25 May 1995
  • Firstpage
    196
  • Lastpage
    200
  • Abstract
    A self-aligned latch-free IGBT, where a trench is located in the middle of p- body, has been proposed and verified by process and device simulations. No additional mask steps for n+ source, p++ region and source contact are required so that small size body would be obtained. As the n+ source is formed by impurity diffused through the sidewall of the trench in the middle of the body, high latch-up capability may be achieved due to the small body resistance and low emitter efficiency of the parasitic n-p-n transistor. Latch-up current densities higher than 10000 A/cm2 have been achieved by adjusting the process conditions
  • Keywords
    current density; insulated gate bipolar transistors; device simulations; high latchup capability; latch-free IGBT; latch-up current density; self-aligned IGBT; sidewall diffused n+ emitter; Current density; Diffusion processes; Doping; Equivalent circuits; Etching; Immune system; Insulated gate bipolar transistors; MOSFET circuits; Silicon; Voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Power Semiconductor Devices and ICs, 1995. ISPSD '95., Proceedings of the 7th International Symposium on
  • Conference_Location
    Yokohama
  • ISSN
    1063-6854
  • Print_ISBN
    0-7803-2618-0
  • Type

    conf

  • DOI
    10.1109/ISPSD.1995.515034
  • Filename
    515034