DocumentCode
2366247
Title
On resistance-leakage current trade-off in low-voltage power PMOSFETs
Author
Darwish, Mohamed N. ; Williams, Richard K. ; Shekar, M.S. ; Chan, T.Y.
Author_Institution
Siliconix Inc., Santa Clara, CA, USA
fYear
1995
fDate
23-25 May 1995
Firstpage
261
Lastpage
266
Abstract
The trade-offs that impact minimizing on-resistance while maintaining an acceptable level of leakage current in very low on-resistance buried p-channel MOSFETs are investigated. Gate induced drain leakage (GIDL) current in power PMOSFETs is studied both experimentally and by using numerical simulations. The effect of several carrier generation mechanisms such as band-to-band tunneling, avalanche multiplication and thermal generation on leakage current are also discussed
Keywords
leakage currents; power MOSFET; avalanche multiplication; band-to-band tunneling; buried p-channel MOSFET; carrier generation; gate induced drain leakage current; low-voltage power PMOSFET; numerical simulation; on-resistance; thermal generation; Charge carrier processes; Current density; Energy management; Immune system; Leakage current; MOSFETs; Numerical simulation; Personal communication networks; Tunneling; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Power Semiconductor Devices and ICs, 1995. ISPSD '95., Proceedings of the 7th International Symposium on
Conference_Location
Yokohama
ISSN
1063-6854
Print_ISBN
0-7803-2618-0
Type
conf
DOI
10.1109/ISPSD.1995.515046
Filename
515046
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