Thin-film SOI power MOSFET design based on emission microscopy

Author

Matsumoto, Satoshi ; Fukumitsu, Takao ; Kim, II-Jung ; Sakai, Tatsuo ; Yachi, Toshiaki

Author_Institution

NTT Interdisciplinary Res. Labs, Tokyo, Japan

fYear

1995

fDate

23-25 May 1995

Firstpage

460

Lastpage

465

Abstract

We have designed an improved 200-V-class thin-film SOI power MOSFET with a stripe-gate topology. A fabricated new device attained a breakdown voltage of 210 V and a specific on-resistance of 2.7 Ω·mm². The new device structure is designed based on the results of emission microscopy analysis of the avalanche breakdown points of devices with stripe-gate and cellular-gate topologies. In the standard stripe-gate topology, the avalanche breakdown occurred at the LOCOS edge of the drain offset region. We raised the breakdown voltage by additional phosphorus ion implantation at this site

Keywords

avalanche breakdown; electron microscopy; ion implantation; photoemission; power MOSFET; silicon-on-insulator; thin film transistors; 200 V; LOCOS; avalanche breakdown; cellular gate; emission microscopy; on-resistance; phosphorus ion implantation; stripe gate; thin-film SOI power MOSFET; Avalanche breakdown; Dielectric thin films; Electric breakdown; MOSFET circuits; Microscopy; Parasitic capacitance; Power MOSFET; Semiconductor thin films; Topology; Transistors;

fLanguage

English

Publisher

ieee

Conference_Titel

Power Semiconductor Devices and ICs, 1995. ISPSD '95., Proceedings of the 7th International Symposium on

Conference_Location

Yokohama

ISSN

1063-6854

Print_ISBN

0-7803-2618-0

Type

conf

DOI

10.1109/ISPSD.1995.515082

Filename

515082