Delay test pattern generation considering crosstalk-induced effects

Author

Li, Huawei ; Zhang, Yue ; Li, Xiaowei

Author_Institution

Inst. of Comput. Technol., Chinese Acad. of Sci., Beijing, China

fYear

2003

fDate

16-19 Nov. 2003

Firstpage

178

Lastpage

183

Abstract

Current design trends have shown that crosstalk issues in deep sub-micron can cause severe design validation and test problems. This paper addresses the problem of delay testing considering crosstalk-induced delay effects. A delay test pattern generation technique is proposed based on waveform sensitization. Crosstalk-induced effects on critical paths are targeted to improve test effectiveness of delay testing. Experimental results show the efficiency of this technique. It can be applied to circuits of reasonable sizes by generating delay tests considering crosstalk-induced effects within an acceptable amount of time.

Keywords

VLSI; automatic test pattern generation; crosstalk; hazards and race conditions; integrated circuit noise; integrated circuit testing; logic testing; timing; VLSI; automatic test pattern generation; critical paths; crosstalk-induced effects; deep submicron technology; delay test pattern generation; design validation; fault selection process; logical path under test; signal integrity; test effectiveness; waveform sensitization; Automatic test pattern generation; Circuit testing; Clocks; Computers; Content addressable storage; Crosstalk; Delay effects; Integrated circuit noise; Integrated circuit testing; Logic circuit testing; Propagation delay; Test pattern generators; Timing; Very-large-scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Symposium, 2003. ATS 2003. 12th Asian

ISSN

1081-7735

Print_ISBN

0-7695-1951-2

Type

conf

DOI

10.1109/ATS.2003.1250806

Filename

1250806