Effects of technology and dimensional scaling on input loss prediction of RF MOSFETs

In this paper, we present the impact of both process and dimensional scaling on input loss (S₁₁) prediction of MOSFET´s at GHz frequencies. We study the distributed gate effect, the non-quasi static effect, and report a drop in the resistive component of S₁₁ for larger fingered devices at high frequencies (> 5 GHz). We identify the boundary at which such effects start dominating. A modification to the existing lumped model is presented that tracks this effect with high accuracy. The impact of oxide thickness on S₁₁ in the same process and across two different processes is also presented. The study was validated with the fabrication of an extensive set of RF dimensioned transistors in LSI Logic´s 0.18 μm and 0.11 μm processes, across five different wafers.