Compact modeling and analysis of coupling noise induced by through-Si-vias in 3-D ICs

Through-silicon vias (TSVs) in 3-D ICs, which are used for connecting different active layers, introduce an important source of coupling noise arising from electromagnetic (EM) coupling between TSVs and the active regions. This work, for the first time, presents compact models based on fully analytical approach for the EM coupling from a TSV to the active regions for a comprehensive set of 3-D IC substrate technologies including those with and without the high conductivity buried layer in dual-well bulk CMOS. The models can be used during design validation of emerging 3-D ICs. The compact physical models are verified against full-wave EM simulations. A comparative analysis of the magnitude of the EM-coupling noise for different 3-D technology scenarios, including both dual-well bulk CMOS and partially-depleted silicon-on-insulator (SOI) is also presented. The compact models presented for dual-well bulk CMOS are subsequently employed for estimating the stay-away radius (safe distance) from the center of the TSVs to the active regions to minimize the impact of such coupling noise.