Characterization and modeling methodology for IC’s ESD susceptibility at system level using VF-TLP tester

Author

Lacrampe, Nicolas ; Caignet, Fabrice ; Bafleur, Marise ; Nolhier, Nicolas ; Mauran, Nicolas

Author_Institution

Univ. de Toulouse, Toulouse

fYear

2007

fDate

16-21 Sept. 2007

Abstract

This paper presents various injection methods aimed at predicting the susceptibility of integrated circuits against electrostatic discharge (ESD) stresses. A very fast transmission line pulsing (VF-TLP) tester is used to inject a disturbance into an IC under operation. A system failure criterion is chosen and a critical stress level is extracted. A modeling methodology is also developed to precisely describe each part of the set up and provide a complete model that describes the IC response to ESD indirect effects.

Keywords

electrostatic discharge; integrated circuit modelling; integrated circuit testing; ESD susceptibility; VF-TLP tester; critical stress level; electrostatic discharge; injection methods; integrated circuits; modeling methodology; system failure criterion; system level; very fast transmission line pulsing tester; Circuit testing; Electrostatic discharge; Immunity testing; Integrated circuit modeling; Integrated circuit testing; Power system reliability; Power transmission lines; Predictive models; Stress; System testing;

fLanguage

English

Publisher

ieee

Conference_Titel

29th Electrical Overstress/Electrostatic Discharge Symposium, 2007. EOS/ESD

Conference_Location

Anaheim, CA

Print_ISBN

978-1-58537-136-5

Type

conf

DOI

10.1109/EOSESD.2007.4401767

Filename

4401767