DocumentCode
2368704
Title
Equivalence checking using independent cuts [logic design verification]
Author
Xu, Zhan ; Yan, Xiaolang ; Lu, Yongjiang ; Ge, Haitong
Author_Institution
Inst. of VLSI Design, Zhejiang Univ., Hangzhou, China
fYear
2003
fDate
16-19 Nov. 2003
Firstpage
482
Lastpage
485
Abstract
With the increase in the complexity of present day systems, proving the correctness of a design has become a major concern. This paper describes a novel implementation of a BDD-based combinational equivalence checking (CEC) tool, which is distinguished from others by one heuristic. It is proposed to select an effective cut, with no dependence remaining. In addition, successfully verification of all the ISCAS´85 benchmark circuits demonstrates the efficiency of our approach.
Keywords
binary decision diagrams; formal verification; heuristic programming; logic design; logic testing; BDD CEC tool; combinational equivalence checking tool; equivalence checking independent cuts; heuristics; logic design verification; Automatic test pattern generation; Binary decision diagrams; Boolean functions; Circuit simulation; Combinational circuits; Data structures; Engines; Explosions; Logic circuit testing; Logic design; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Symposium, 2003. ATS 2003. 12th Asian
ISSN
1081-7735
Print_ISBN
0-7695-1951-2
Type
conf
DOI
10.1109/ATS.2003.1250864
Filename
1250864
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