A test architecture for system-on-a-chip

Author

Yong-sheng, Wang ; Li-yi, Xiao ; Ming-yan, Yu ; Jin-xiang, Wang ; Yi-zheng, Ye

Author_Institution

Microelectron. Center, Harbin Inst. of Technol., China

fYear

2003

fDate

16-19 Nov. 2003

Firstpage

506

Abstract

This paper proposes a configurable TAM-Bus, a P1500 compliant Test Access Mechanism (TAM), and the TAM-Bus controller (TAM-controller) that is interfaced with JTAG at chip level of chip. All IP (Intellectual Property) cores´ test can be controlled through the TAP under the control of the TAM-controller. The test architecture we presented has been implemented in an industry SoC. The test coverage remains 99.40%. The overhead increases only 0.17% due to TAM. The experiment results demonstrate that the test architecture can offer the solution for testing SoC.

Keywords

boundary scan testing; built-in self test; integrated circuit testing; system-on-chip; Intellectual Property cores; JTAG; TAM-Bus controller; boundary scan operation; chip-level controller; compliant test access mechanism; configurable TAM-Bus; system-on-a-chip; test architecture; Boundary scan testing; Chromium; Circuit testing; Computer architecture; Integrated circuit testing; Intellectual property; Microelectronics; Performance evaluation; Registers; Self-testing; Standards development; System testing; System-on-a-chip;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Symposium, 2003. ATS 2003. 12th Asian

ISSN

1081-7735

Print_ISBN

0-7695-1951-2

Type

conf

DOI

10.1109/ATS.2003.1250875

Filename

1250875