• DocumentCode
    2369161
  • Title

    A novel low-voltage biasing scheme for double gate FBC achieving 5s retention and 1016 endurance at 85°C

  • Author

    Lu, Z. ; Collaert, N. ; Aoulaiche, M. ; De Wachter, B. ; De Keersgieter, An ; Schwarzenbach, W. ; Bonnin, O. ; Bourdelle, K.K. ; Nguyen, B.Y. ; Mazure, C. ; Altimime, L. ; Jurczak, M.

  • Author_Institution
    Imec, Leuven, Belgium
  • fYear
    2010
  • fDate
    6-8 Dec. 2010
  • Abstract
    We demonstrate a novel low-voltage biasing scheme on ultra-thin BOX (UTBOX) FDSOI floating body cells with Lg=55nm and tSi=20nm. By optimizing the front and back gate biasing to enhance the positive feedback loop, the required VDS can be reduced to 1.5V while retention times as high as 5s can still be achieved at 85°C. For the first time, we also show that the stringent endurance spec of 1016 cycles can be met as a result of the VDS reduction.
  • Keywords
    DRAM chips; low-power electronics; silicon-on-insulator; double gate FBC; low-voltage biasing scheme; temperature 85 degC; time 5 s; ultra-thin BOX FDSOI floating body cells;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electron Devices Meeting (IEDM), 2010 IEEE International
  • Conference_Location
    San Francisco, CA
  • ISSN
    0163-1918
  • Print_ISBN
    978-1-4424-7418-5
  • Electronic_ISBN
    0163-1918
  • Type

    conf

  • DOI
    10.1109/IEDM.2010.5703347
  • Filename
    5703347
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2369161