• DocumentCode
    236960
  • Title

    Package technology evaluation and optimization for high-speed applications

  • Author

    Lo, Leung-Yau ; Cheah, Bok Eng

  • Author_Institution
    Intel Corp., Folsom, CA, USA
  • fYear
    2014
  • fDate
    4-8 Aug. 2014
  • Firstpage
    625
  • Lastpage
    630
  • Abstract
    This paper analyzes the electrical performance of standard and coreless packages up-to 100Gbps data rate. The impact of package design attributes e.g. substrate core thickness, plated through hole (PTH) pad dimension and geometry of second level interconnect (SLI) on insertion loss performance are explored in this study. This study also evaluates the electrical performance of an alternative coreless package solution with metal grid array (MGA) SLI to enable ultra-thin and small form factor electronic devices. In addition to the advantages of configurable and scalable SLI geometry, the full-wave electromagnetic simulation results shows significant insertion loss performance improvement with MGA coreless package as the frequency increases. The root-causes of insertion loss degradations among the evaluated packaging solutions were identified and further discussed in this paper.
  • Keywords
    ball grid arrays; electronics packaging; interconnections; full-wave electromagnetic simulation; insertion loss; metal grid array; package design; package technology evaluation; plated through hole pad dimension; second level interconnect; small form factor electronic devices; substrate core thickness; Geometry; Impedance; Insertion loss; Packaging; Performance evaluation; Standards; Substrates;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electromagnetic Compatibility (EMC), 2014 IEEE International Symposium on
  • Conference_Location
    Raleigh, NC
  • Print_ISBN
    978-1-4799-5544-2
  • Type

    conf

  • DOI
    10.1109/ISEMC.2014.6899046
  • Filename
    6899046