DocumentCode
2370381
Title
A novel low power 16×16 content addressable memory using PAL
Author
Bala, G. Josemin ; Perinbam, J. Raja Paul
Author_Institution
Dept. of Electron. & Commun. Eng., Anna Univ., India
fYear
2005
fDate
3-7 Jan. 2005
Firstpage
791
Lastpage
794
Abstract
This paper presents a novel low power content addressable memory (CAM) using pass transistor adiabatic logic (PAL). The PAL CAM uses adiabatic principle in the read, write and compare operations. The SPICE simulation of 16×16 CAM indicates around 95% of power saving at 10MHz operating frequency compared to conventional design. The circuits are designed using 0.6μm CMOS technology.
Keywords
SPICE; content-addressable storage; logic design; low-power electronics; 0.6 micron; 10 MHz; CAM; CMOS technology; PAL; SPICE simulation; circuit design; compare operation; content addressable memory; pass transistor adiabatic logic; power saving; read operation; write operation; Associative memory; CADCAM; Circuit simulation; Clocks; Computational modeling; Computer aided manufacturing; Embedded system; Logic; Random access memory; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Design, 2005. 18th International Conference on
ISSN
1063-9667
Print_ISBN
0-7695-2264-5
Type
conf
DOI
10.1109/ICVD.2005.27
Filename
1383371
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