• DocumentCode
    2371776
  • Title

    A built-in IDDQ test circuit utilizing upper and lower limits

  • Author

    Miura, Yukiya ; Naito, Sachio

  • Author_Institution
    Dept. of Electron. & Inf. Eng., Tokyo Metropolitan Univ., Japan
  • fYear
    1994
  • fDate
    15-17 Nov 1994
  • Firstpage
    138
  • Lastpage
    143
  • Abstract
    A test circuit for the built-in IDDQ testing is proposed. The circuit can use two current values, an upper limit and a lower limit, to judge whether CUT is fault-free or not. The test circuit is applicable to fault detection for both digital and analog circuits. We show the efficiency of the test circuit using SPICE3 simulator
  • Keywords
    CMOS digital integrated circuits; CMOS integrated circuits; SPICE; built-in self test; electric current measurement; fault location; integrated circuit testing; mixed analogue-digital integrated circuits; IDDQ test circuit; SPICE3 simulator; analog circuits; built in test; digital CMOS circuits; digital circuits; fault detection; lower limits; mixed signal CMOS circuits; upper limits; Analog circuits; CMOS digital integrated circuits; Circuit faults; Circuit simulation; Circuit testing; Current measurement; Digital circuits; Electrical fault detection; Electrical resistance measurement; Electronic equipment testing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Test Symposium, 1994., Proceedings of the Third Asian
  • Conference_Location
    Nara
  • Print_ISBN
    0-8186-6690-0
  • Type

    conf

  • DOI
    10.1109/ATS.1994.367240
  • Filename
    367240
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2371776