Efficiency improvements for multiple fault diagnosis of combinational circuits

Author

Yanagida, Nobuhiro ; Takahashi, Hiroshi ; Takamatsu, Yuzo

Author_Institution

Dept. of Comput. Sci., Ehime Univ., Matsuyama, Japan

fYear

1994

fDate

15-17 Nov 1994

Firstpage

82

Lastpage

87

Abstract

We present two techniques for improving the efficiency of the previous method for multiple fault diagnosis of combinational circuits. (1) Three new rules for deducing the valves at the internal lines are added to the previous deduction rules. Experimental results show that 2.6~15.2% improvements in resolution are achieved by adding the enhanced deduction rules without probing the internal lines. (2) A probing method for diagnosis is proposed to improve the resolution obtained by the method (1). Preliminary experimental results show that about 0.1~9.4% improvements in resolution are further achieved by probing about 4~111 internal lines in the circuit

Keywords

VLSI; combinational circuits; fault diagnosis; fault location; integrated circuit testing; integrated logic circuits; logic testing; combinational circuits; deduction rules; efficiency; enhanced deduction rules; internal lines; multiple fault diagnosis; probing method; Circuit faults; Circuit testing; Combinational circuits; Computer science; Dictionaries; Fault diagnosis; Large scale integration; Logic circuits; Logic testing; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Symposium, 1994., Proceedings of the Third Asian

Conference_Location

Nara

Print_ISBN

0-8186-6690-0

Type

conf

DOI

10.1109/ATS.1994.367249

Filename

367249