Investigation on TSV impact on 65nm CMOS devices and circuits

Author

Chaabouni, H. ; Rousseau, M. ; Leduc, P. ; Farcy, A. ; El Farhane, R. ; Thuaire, A. ; Haury, G. ; Valentian, A. ; Billiot, G. ; Assous, M. ; de Crecy, F. ; Cluzel, J. ; Toffoli, A. ; Bouchu, D. ; Cadix, L. ; Lacrevaz, T. ; Ancey, P. ; Sillon, N. ; Flechet

Author_Institution

LETI, CEA, Grenoble, France

fYear

2010

fDate

6-8 Dec. 2010

Abstract

4μm wide copper Through Silicon Vias (TSV) were processed on underlying 65nm CMOS devices and circuits in order to evaluate the impact of the three-dimensional (3D) integration process. Electrical tests on isolated MOSFET and ring oscillators in the presence of TSVs are compared to modeling results. Beside TSV mechanical impact, an electrical coupling between TSV and MOSFET is experimentally quantified and reported for the first time. This coupling induces a spike variation up to 7μA/μm on the static NMOS drain current. However, the ring oscillators response is not impacted.

Keywords

CMOS integrated circuits; MOSFET; copper; impact (mechanical); oscillators; three-dimensional integrated circuits; CMOS circuits; CMOS devices; Cu; Si; TSV mechanical impact; copper through silicon vias; electrical coupling; isolated MOSFET; ring oscillators; size 4 mum; size 65 nm; static NMOS drain current; three-dimensional integration process;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting (IEDM), 2010 IEEE International

Conference_Location

San Francisco, CA

ISSN

0163-1918

Print_ISBN

978-1-4424-7418-5

Electronic_ISBN

0163-1918

Type

conf

DOI

10.1109/IEDM.2010.5703479

Filename

5703479