Delay Matching Compensated CMOS Microwave Frequency Doubler

Author

Song, Kyungju ; Choi, Heungjae ; Kim, Chul Dong ; Kenney, J.S. ; Jeong, Yongchae

Author_Institution

Dept. of Inf. & Commun. Eng., Chonbuk Nat. Univ., Jeonju

fYear

2008

fDate

27-31 Oct. 2008

Firstpage

464

Lastpage

467

Abstract

In this paper, a modified time-delay microwave frequency doubler is proposed. A voltage controlled delay line (VCDL) in the proposed frequency doubler compensates the time-delay mismatching between input and delayed signal. With the delay matching and waveform shaping using adjustable Schmitt triggers, the unwanted fundamental component (f₀) and the higher order harmonics such as third and fourth are diminished excellently. In result, only the doubled frequency component (2f₀) appears dominantly at the output port. The frequency doubler is designed at 1.15 GHz of f₀ and fabricated with TSMC 0.18 mum CMOS process. The measured output power of 2f₀ is 2.67 dBm when the input power is 0 dBm. The obtained suppression of f₀, 3f₀, and 4f₀ to 2f₀ are 43.65, 38.65 and 35.59 dB, respectively.

Keywords

CMOS logic circuits; UHF integrated circuits; delay lines; frequency multipliers; harmonics suppression; integrated circuit design; logic design; microwave integrated circuits; trigger circuits; CMOS time-delay microwave frequency doubler; Schmitt triggers; TSMC CMOS process; delay matching; frequency 1.15 GHz; higher-order harmonics supression; size 0.18 mum; voltage controlled delay line; waveform shaping; Delay lines; Inverters; Microwave frequencies; Phase locked loops; Power generation; Power harmonic filters; Propagation delay; Timing; Trigger circuits; Voltage control;

fLanguage

English

Publisher

ieee

Conference_Titel

Microwave Conference, 2008. EuMC 2008. 38th European

Conference_Location

Amsterdam

Print_ISBN

978-2-87487-006-4

Type

conf

DOI

10.1109/EUMC.2008.4751489

Filename

4751489