5GHz 32b integer-execution core in 130nm dual-V/sub T/ CMOS

Author

Vangal, S. ; Borkar, N. ; Seligman, E. ; Govindarajulu, V. ; Erraguntla, V. ; Wilson, H. ; Pangal, A. ; Veeramachaneni, V. ; Anders, M. ; Tschanz, J. ; Ye, Y. ; Somasekhar, D. ; Bloechel, B. ; Dermer, G. ; Krishnamurthy, R. ; Narendra, S. ; Stan, M. ; Tho

Author_Institution

Intel Corporation

Volume

fYear

2002

fDate

7-7 Feb. 2002

Firstpage

334

Lastpage

535

Keywords

Adders; Circuit testing; Clocks; Delay; Flip-flops; Prototypes; Radio frequency; Registers; Signal design; Signal generators;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2002. Digest of Technical Papers. ISSCC. 2002 IEEE International

Conference_Location

San Francisco, CA, USA

Print_ISBN

0-7803-7335-9

Type

DOI

10.1109/ISSCC.2002.992282

Filename

992282

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