A 180 nm low power CMOS operational amplifier

Author

Raut, Ketan J. ; Kshirsagar, R.V. ; Bhagali, A.C.

Author_Institution

Dept. of E&TC Eng., Vishwakarma Inst. of Inf. Technol., Pune, India

fYear

2014

fDate

28-29 Nov. 2014

Firstpage

341

Lastpage

344

Abstract

This paper presents the design of two-stage operational amplifier (Op Amp). The circuit was designed in standard 180 nm digital n-well CMOS process. The design consists of very less number of transistors, hence the design is area optimized. Achieved open loop gain of the amplifier is 74.89 dB. The unity gain bandwidth (UGB) is 7.3 MHz and the phase margin is 48 degree with a 10 pF capacitive and 1 M ohm resistive load. The average power consumption of the amplifier is 0.402 mW and slew rate is 10 V/us.

Keywords

CMOS digital integrated circuits; integrated circuit design; low-power electronics; operational amplifiers; Op Amp; UGB; bandwidth 7.3 MHz; capacitance 10 pF; digital n-well CMOS process; gain 74.89 dB; low power CMOS operational amplifier; open loop gain; phase margin; power 0.402 mW; power consumption; resistance 1 Mohm; size 180 nm; two-stage operational amplifier; unity gain bandwidth; Bandwidth; CMOS integrated circuits; Gain; Operational amplifiers; Power dissipation; Simulation; Topology; CMOS Op Amp; Low Power; Moderate Speed;

fLanguage

English

Publisher

ieee

Conference_Titel

Computational Intelligence on Power, Energy and Controls with their impact on Humanity (CIPECH), 2014 Innovative Applications of

Conference_Location

Ghaziabad

Type

conf

DOI

10.1109/CIPECH.2014.7019049

Filename

7019049