Phase correction of a resonant clocking system using resonant interpolators

Large static phase errors result from injection-locked LC clock buffers due to slight frequency mismatch between the input frequency and the tankpsilas resonant frequency. The paper demonstrates a technique that embeds a resonant interpolator into the clock buffer to correct the phase error without additional buffer elements. The test chip is fabricated in a 0.13 mum digital CMOS technology. Measured DNL of the resonant interpolator is <0.6 LSB even with quadrature inputs and phase error <1 ps is achieved.