Impedance Matching Techniques in 65nm CMOS Power Amplifiers for 2.4GHz 802.11n WLAN

Author

Fritzin, Jonas ; Johansson, Ted ; Alvandpour, Atila

Author_Institution

Dept. of Electr. Eng., Linkoping Univ., Linkoping

fYear

2008

fDate

27-31 Oct. 2008

Firstpage

1207

Lastpage

1210

Abstract

This paper describes the design of two power amplifiers (PA) for WLAN 802.11n fabricated in 65 nm CMOS technology. Both PAs utilize 3.3V thick-gate oxide (5.2 nm) transistors and employ a two-stage differential structure, but the input and interstage matching networks are realized differently. The first PA uses LC matching networks for matching, while the second PA uses on-chip transformers. The impedance matching techniques applied for the matching networks will be described. EVM, output power levels, and spectral masks are obtained for a 72.2 Mbit/s, 64-QAM, 802.11n, OFDM signal.

Keywords

CMOS integrated circuits; impedance matching; power amplifiers; transformers; transistors; wireless LAN; CMOS power amplifiers; OFDM signal; WLAN; frequency 2.4 GHz; impedance matching; interstage matching networks; on-chip transformers; output power levels; spectral masks; thick-gate oxide; transistors; two-stage differential structure; CMOS technology; Differential amplifiers; Impedance matching; Indium phosphide; Microwave amplifiers; Network-on-a-chip; Power amplifiers; Radiofrequency amplifiers; Transformers; Wireless LAN; CMOS analog integrated circuits; baluns; impedance matching; power amplifiers; transformers;

fLanguage

English

Publisher

ieee

Conference_Titel

Microwave Conference, 2008. EuMC 2008. 38th European

Conference_Location

Amsterdam

Print_ISBN

978-2-87487-006-4

Type

conf

DOI

10.1109/EUMC.2008.4751677

Filename

4751677