DocumentCode
2376127
Title
A 9.4-bit, 50-MS/s, 1.44-mW pipelined ADC using dynamic residue amplification
Author
Hu, Jason ; Dolev, Noam ; Murmann, Boris
Author_Institution
Stanford Univ., Stanford, CA
fYear
2008
fDate
18-20 June 2008
Firstpage
216
Lastpage
217
Abstract
An ultra-low power pipelined ADC is realized by replacing conventional op-amp circuits with dynamic source-follower gain stages. The presented 90-nm CMOS converter operates at 50 MS/s and achieves an SNDR of 49.4 dB while dissipating 1.44 mW from a 1.2-V supply.
Keywords
CMOS analogue integrated circuits; analogue-digital conversion; operational amplifiers; CMOS converter; dynamic residue amplification; dynamic source-follower gain stages; noise figure 49.4 dB; op-amp circuits; power 1.44 mW; size 90 nm; ultralow power pipelined ADC; voltage 1.2 V; Circuit topology; Clocks; Operational amplifiers; Pipelines; Power amplifiers; Power dissipation; Sampling methods; Switched capacitor circuits; Switches; Voltage; CMOS; pipelined ADC; source follower and dynamic amplifier; switched-capacitor circuits;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Circuits, 2008 IEEE Symposium on
Conference_Location
Honolulu, HI
Print_ISBN
978-1-4244-1804-6
Electronic_ISBN
978-1-4244-1805-3
Type
conf
DOI
10.1109/VLSIC.2008.4586012
Filename
4586012
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