A novel 7T SRAM cell design for reducing Leakage Power and improved stability

As the channel length of MOSFETs is scaling down, the Leakage Power and the stability of the SRAM cells become the major concern for future technology. In this paper, stable SRAM cell is proposed which improves the stability of the SRAM cell and reduces the average power dissipation during the read write operation and reduces the leakage power in standby mode. Two techniques for reducing gate leakage currents and sub threshold leakage currents are examined. In first technique, the supply voltage is decreased. In the second techniques the voltage of the ground node is increased and hence the effective voltage across SRAM cell is decreased. The proposed SRAM cell is compared to conventional 6T SRAM cell in terms of power consumption and delay. The proposed SRAM cell consumes 60-70% less power for read and write operations and 40-60% reduction in leakage power has been observed. The speed, however, is degraded by 30-40% in the SRAM cells. The simulations are carried out in Tanner EDA tool with 180nm and 45nm technologies at 1.8V and 1V power supply respectively.