ECC: extended condition coverage for design verification using excitation and observation

An important issue in register-transfer-level (RTL) hardware verification is the ability to check specified functions and to determine the presence of an error. Code-level coverage is often used to measure the success in verification at this level. However existing code-level coverage inaccurately estimates the verification result by considering only the excitations of functional blocks. While it may be impossible to achieve 100% correctness with code-coverage measure, checking excitation of functions and monitoring the effects at output ports can improve reliability of functional verification. This paper presents an RTL functional verification approach that evaluates the excitation-states of conditional expressions and propagates the excited information to output ports. The proposed approach with Verilog PLI-based implementation provide more meaningful coverage value that can measure the extent of functional verification in a very effective way during logic simulation