An ATPG for threshold testing: obtaining acceptable yield in future processes

Author

Jiang, Zhigang ; Gupta, Sandeep K.

Author_Institution

Dept. of Electron. Eng. Syst., Univ. of Southern California, Los Angeles, CA, USA

fYear

2002

fDate

2002

Firstpage

824

Lastpage

833

Abstract

When VLSI scaling reaches closer to the limits of laws of physics and to the limits of fabrication processes, yields will decrease, especially at desired speed. However, for a large class of applications, chips need not be perfect to be acceptable. In this paper, we describe the notion of threshold testing that can help improve effective yield for future processes. We then develop an ATPG and demonstrate that significant increase in effective yield can be attained at negligible increase in test application cost.

Keywords

VLSI; automatic test pattern generation; digital integrated circuits; integrated circuit testing; integrated circuit yield; logic testing; production testing; ATPG algorithm; VLSI circuits; VLSI scaling; acceptable faults identification; acceptable yield; digital chips; test application cost; threshold ATPG; threshold testing; yield improvement; Automatic test pattern generation; Circuit faults; Digital circuits; Fabrication; Parallel architectures; Semiconductor device measurement; Testing; Transform coding; Very large scale integration; Video compression;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Conference, 2002. Proceedings. International

ISSN

1089-3539

Print_ISBN

0-7803-7542-4

Type

conf

DOI

10.1109/TEST.2002.1041836

Filename

1041836