DocumentCode
2379475
Title
Wireless SOC testing: Can RF testing costs be reduced?
Author
Kafton, Alan
Author_Institution
Wireless Semicond. Test Solutions, Agilent Technol., Santa Rosa, CA, USA
fYear
2002
fDate
2002
Firstpage
1226
Abstract
Emerging wireless SOCs and SiPs are highly integrated devices containing logic, analog, RF, and even memory blocks. From a pure "can it be tested?" point of view, engineers are faced with a number of testing challenges. Add to that the economic challenges and the test community must find ways to test increasingly complex devices AND reduce cost of test. When approaching test, it is important to determine acceptable methodologies. For the purpose of this discussion, I propose three possible scenarios: 1) fault testing to verify that manufacturing processes produce a defect-free product; 2) functional testing to verify the SOC functions as intended; and 3) performance-based testing to verify the SOC meets published specs.
Keywords
analogue integrated circuits; fault location; formal verification; integrated circuit economics; integrated circuit testing; integrated memory circuits; logic circuits; performance evaluation; radiofrequency integrated circuits; system-on-chip; IC test economics; RF test capability; SOC function verification; SOC specification verification; SiP; complex device testing; cost cutting methodologies; defect-free products; fault testing; functional testing; logic/analog/RF/memory blocks; manufacturing process verification; performance-based testing; system-in-package; system-on-chip; test cost reduction; wireless SOC RF testing; Bluetooth; Circuit faults; Circuit testing; Costs; Hardware; Logic testing; Performance evaluation; Radio frequency; Semiconductor device testing; System testing;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Conference, 2002. Proceedings. International
ISSN
1089-3539
Print_ISBN
0-7803-7542-4
Type
conf
DOI
10.1109/TEST.2002.1041928
Filename
1041928
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