DocumentCode
2381128
Title
Effect of sputtered TiW deposition conditions on barrier properties for submicron metallization
Author
Georgiou, G.E. ; Baker, M. ; Eshraghi, S.A.
Author_Institution
AT&T Bell Labs., Murray Hill, NJ, USA
fYear
1991
fDate
11-12 Jun 1991
Firstpage
420
Lastpage
422
Abstract
Reports the results of an orthogonal array study of the step coverage of magnetron sputtered TiW. The authors concentrate on the effect of target power (1-2.5 kW), Ar pressure (4-21 mT), and substrate temperature (100-450°C) on coverage into near vertical wall windows (85° wall angle) with aspect ratio ~1.5 (h/w=1.3/0.85) reactive ion etched in a deposited oxide. Scanning electron microscopy (SEM) indicates that coverage defined as the ratio of TiW~1000 Å thick on top of oxide to that in the bottom of the windows, varies between ~25-35%. Coverage improves with moderate power ~2 kW and temperature ~300°C. Ar pressure has a somewhat smaller effect on coverage than either power or temperature. TiW resistivity and stress magnitude also decrease to 0.65-0.7 μΩ-cm and low 109 dynes/cm2 respectively, for the sputtering conditions used to maximize step coverage. Reverse bias diode leakage (~3000 Å deep n +/p with ~1000 Å TiSi2 and window contacts) does not degrade for Al/TiW or Al/CVD W/TiW metallization of the window contacts are annealed at 450°C, 30 min., the highest anneal cycle used in this study. Low leakage was measured for a nominal 1000 Å thick TiW deposited with the conditions giving the best and worst window coverage, indicating that ~300 Å is an acceptable barrier at ⩽450°C
Keywords
VLSI; metallisation; reliability; sputtered coatings; titanium alloys; tungsten alloys; 0.65 to 0.7 muohmcm; 0.85 micron; 1 to 2.5 kW; 100 to 450 C; 1000 to 300 A; 4 to 21 mtorr; Ar pressure; SEM; TiW deposition conditions; VLSI; aspect ratio; barrier properties; multilevel interconnection; near vertical wall windows; orthogonal array study; resistivity; sputtering conditions; step coverage; stress magnitude; submicron metallization; submicron vias; substrate temperature; target power; window contacts; Annealing; Argon; Conductivity; Degradation; Diodes; Scanning electron microscopy; Sputter etching; Sputtering; Stress; Temperature;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Multilevel Interconnection Conference, 1991, Proceedings., Eighth International IEEE
Conference_Location
Santa Clara, CA
Print_ISBN
0-87942-673-X
Type
conf
DOI
10.1109/VMIC.1991.153044
Filename
153044
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