A 1 V CMOS PLL designed in high-leakage CMOS process operating at 10-700 MHz

Author

Holzer, R.

Author_Institution

DSP Design Center, Analog Devices Inc., Herzlia, Israel

Volume

1

fYear

2002

fDate

7-7 Feb. 2002

Firstpage

272

Abstract

A PLL is fabricated in a 0.13 /spl mu/m logic process where leakage currents are high. The loop capacitor is implemented by a structure of poly and 9 metal layers. The VCO is implemented with common-mode feedback to compensate for leakage currents. Maximum VCO frequency is 1400 MHz. Typical power is 7 mW at 200 MHz. RMS jitter is 25.4 ps at 360 MHz.

Keywords

CMOS integrated circuits; compensation; feedback oscillators; integrated circuit design; integrated circuit measurement; jitter; leakage currents; phase locked loops; voltage-controlled oscillators; 0.13 micron; 1 V; 10 to 700 MHz; 1400 MHz; 200 MHz; 360 MHz; 7 mW; CMOS PLL; VCO common-mode feedback; high-leakage CMOS process; jitter; leakage current compensation; leakage currents; logic process; loop capacitor; maximum VCO frequency; operating frequency; poly/metal layer structure; power dissipation; CMOS process; Capacitance; Capacitors; Charge pumps; Delay; Leakage current; Phase locked loops; Video recording; Voltage control; Voltage-controlled oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2002. Digest of Technical Papers. ISSCC. 2002 IEEE International

Conference_Location

San Francisco, CA, USA

Print_ISBN

0-7803-7335-9

Type

conf

DOI

10.1109/ISSCC.2002.993041

Filename

993041