Stacked keeper with body bias: A new approach to reduce leakage power for low power VLSI design

In this paper we present a technique named as stacked keeper with body bias (SK-BB). It uses stack effect to existing sleepy keeper technique along with body bias for ultra low static power consumption. A 4-bit CMOS adder circuit is designed using existing techniques like sleep, zig-zag, sleepy-stack, dual stack, sleepy-keeper and proposed techniques SK-BB and SK-BB with High V_th (SK-BBH). Simulation study shows SK-BB and SK-BBH achieves lowest static power consumption among all above techniques. SK-BB and SK-BBH achieves 53% and 34% of less static power than sleepy keeper approach. The dynamic power of SK-BB and SK-BBH are 1% more and 9% less than sleepy keeper approach. However, the delay of the SK-BB and SK-BBH increases by 59% and 4% than sleepy keeper.