Estimation of delay of signature sequences in coherent chip-asynchronous DS/SS systems

We consider the chip-asynchronous model for which the unknown delay of the received signature sequence is of the form (k+ε)T_c, where k is an integer, ε∈[0, 1) is the fractional delay, and T_c is the chip duration. We assume that a serial search scheme is used to obtain an estimate kˆ of k, and propose schemes which may be used to estimate ε to any specified degree of accuracy simultaneously with the operation of the serial search. Such schemes may be useful in reducing the overall time to synchronization, because the code tracking loop will lock quickly if it is supplied with an accurate estimate of ε (assuming that kˆ=k). We have derived various estimators for ε, and in particular obtained an optimal estimator which is easily implementable and which has the best possible acquisition error probability performance, both in the average and minimax senses. Thus, it is possible to obtain an optimal estimate of ε simultaneously with the operation of the serial search scheme, and at very little extra hardware cost. Some numerical results illustrating the performance of this optimal estimator are provided