DocumentCode
2385430
Title
Combined test structure for systematic and stochastic mosfets and gate resistance process variation assessment
Author
Bortesi, L. ; Vendrame, L. ; Fontana, G.
Author_Institution
Numonyx R&D - Technol. Dev., Agrate Brianza, Italy
fYear
2010
fDate
22-25 March 2010
Firstpage
226
Lastpage
230
Abstract
A powerful and compact test structure based on the combination of mosfet and resistor mismatch-like configurations is presented. This new combined solution helps to assess not only the systematic and stochastic mosfet and gate resistance electrical performance and their process variations but also the dependencies on the environment and the impact of different layout solutions.
Keywords
MOSFET; semiconductor device models; combined test structure; gate resistance electrical performance; gate resistance process variation assessment; layout solutions; process variations; resistor mismatch-like configurations; stochastic MOSFET; systematic MOSFET; Electric resistance; Geometry; MOSFETs; Microelectronics; Research and development; Resistors; Signal processing; Stochastic processes; Stochastic systems; System testing; Mismatch; process variability;
fLanguage
English
Publisher
ieee
Conference_Titel
Microelectronic Test Structures (ICMTS), 2010 IEEE International Conference on
Conference_Location
Hiroshima
Print_ISBN
978-1-4244-6912-3
Electronic_ISBN
978-1-4244-6914-7
Type
conf
DOI
10.1109/ICMTS.2010.5466810
Filename
5466810
Link To Document