Test structures for characterization of thermal-mechanical stress in 3D stacked IC for analog design

Author

Minas, Nikolaos ; Van der Plas, Geert ; Oprins, Herman ; Yang, Yu ; Okoro, Chuckwudi ; Mercha, Abdelkarim ; Cherman, Vladimir ; Torregiani, Cristina ; Perry, Dan ; Cupac, Miro ; Rakowski, Michal ; Marchal, Pol

Author_Institution

IMEC, Leuven, Belgium

fYear

2010

fDate

22-25 March 2010

Firstpage

140

Lastpage

144

Abstract

In this paper we present test structures and measurement techniques that enable extraction of significance of effects expected in 3D TSV technologies. The DAC test structure is optimized to detect Ion changes down to 0.5% due to TSV proximity, TSV orientation, thermal hotspots and wafer thinning/stacking process. The results obtained from the stand-alone MOS devices and the DAC structure clearly indicate the impact of TSV proximity and TSV orientation on the carrier mobility of nearby transistors.

Keywords

analogue integrated circuits; carrier mobility; digital-analogue conversion; integrated circuit testing; thermal management (packaging); three-dimensional integrated circuits; 3D TSV technology; 3D stacked IC; DAC test structure; TSV orientation; TSV proximity; analog design; carrier mobility; measurement technique; stacking process; thermal hotspot; thermal-mechanical stress; wafer thinning; Analog integrated circuits; Integrated circuit testing; Thermal stresses; 3D; Digital to Analog Converters; Thermal-Mechanical stress; analog devices;

fLanguage

English

Publisher

ieee

Conference_Titel

Microelectronic Test Structures (ICMTS), 2010 IEEE International Conference on

Conference_Location

Hiroshima

Print_ISBN

978-1-4244-6912-3

Electronic_ISBN

978-1-4244-6914-7

Type

conf

DOI

10.1109/ICMTS.2010.5466836

Filename

5466836