• DocumentCode
    2386927
  • Title

    Application of Global Loops on ULSI Routing for DfY

  • Author

    Panitz, P. ; Olbrich, M. ; Koehl, J. ; Barke, E.

  • Author_Institution
    Inst. of Microelectron. Syst., Hannover Univ.
  • fYear
    0
  • fDate
    0-0 0
  • Firstpage
    1
  • Lastpage
    4
  • Abstract
    The number of circuit malfunctions due to opens increases with shrinking technologies. This requires reconsidering traditional tree based routing approaches for signal wiring. In this paper, we apply global loops to generate robust net topologies which are fully immune against single open faults. We show that the solution of the traveling salesperson problem yields a nearly optimal solution to the two edge connected subgraph problem. Additionally, we introduce a heuristic for finding additional segments which significantly reduce the delay. As result the critical area reduction is better than in previous published approaches which augment minimum Steiner trees
  • Keywords
    ULSI; integrated circuit design; integrated circuit interconnections; integrated circuit yield; linear programming; travelling salesman problems; tree searching; DfY; ULSI routing; circuit malfunctions; critical area reduction; delay reduction; global loops; open faults; robust net topologies; signal wiring; subgraph problem; traveling salesperson problem; tree-based routing; Circuit faults; Delay; Joining processes; Microelectronics; Network topology; Robustness; Routing; Ultra large scale integration; Wire; Wiring;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Integrated Circuit Design and Technology, 2006. ICICDT '06. 2006 IEEE International Conference on
  • Conference_Location
    Padova
  • Print_ISBN
    1-4244-0097-X
  • Type

    conf

  • DOI
    10.1109/ICICDT.2006.220822
  • Filename
    1669409