An optimized de-synchronization flow for power and performance optimization

The de-synchronization methodology, which directly converts a synchronous circuit into an asynchronous counterpart according to the physical structure of pipelines, is very popular for its simplicity. However, the simplicity of the design methodology also introduces some power redundancy and performance reduction to de-synchronized circuits. This paper firstly investigates the influence of actual operations and operands to desynchronized circuits, and then proposes an optimized de-synchronization flow to resolve the power and performance problems in conventional de-synchronized circuits. At last, some specific schemes which are early completion, decoupling and delay element optimization are employed to optimize a traditional desynchronized multiplier. Compared to a traditional desynchronized multiplier, early completion can achieve as high as 72% power reduction and 54% performance improvement. While the power saving resulting from decoupling is about 20%-25% and performance improvement by optimizing delay elements is about 11%.