DocumentCode
2388399
Title
Characterization of the diode leakage current in advanced 0.12 /spl mu/m CMOS technology. (Does stress play a role?)
Author
Toren, Willem-Jan ; Perrin, Emmanuel ; Lunenborg, Meindert
Author_Institution
Philips Semicond., Crolles, France
fYear
2001
fDate
29-30 Nov. 2001
Firstpage
15
Lastpage
18
Abstract
Anomalous N+/Pwell diode leakage current in advanced 0.12 /spl mu/m CMOS technology is investigated. This current is tunnel enhanced, and geometry dependent. Doping level variations can explain this current behaviour, as well as other width scalable deviations like the mobility. Stress in STI is the most probable cause of these doping variations.
Keywords
CMOS integrated circuits; carrier mobility; integrated circuit technology; internal stresses; isolation technology; leakage currents; semiconductor diodes; semiconductor doping; tunnelling; 0.12 micron; CMOS technology; N+/P-well diode leakage current; STI stress; carrier mobility; doping level; tunnel enhanced current; CMOS technology; Current measurement; Geometry; Leakage current; Photonic band gap; Semiconductor device doping; Semiconductor device modeling; Semiconductor diodes; Stress; Transistors;
fLanguage
English
Publisher
ieee
Conference_Titel
Junction Technology, 2001. IWJT. Extended Abstracts of the Second International Workshop on
Conference_Location
Tokyo, Japan
Print_ISBN
4-89114-019-4
Type
conf
DOI
10.1109/IWJT.2001.993817
Filename
993817
Link To Document