Guideline for Low-temperature-operation Technique to Extend CMOS Scaling

Author

Hokazono, A. ; Kawanaka, S. ; Tsumura, K. ; Hayashi, Y. ; Tanimoto, H. ; Enda, T. ; Aoki, N. ; Ohuchi, K. ; Inaba, S. ; Okano, K. ; Fujiwara, M. ; Morooka, T. ; Goto, M. ; Kajita, A. ; Usui, T. ; Ishimaru, K. ; Toyoshima, Y.

Author_Institution

Semicond. Co., Toshiba Corp., Yokohama

fYear

2006

fDate

11-13 Dec. 2006

Firstpage

1

Lastpage

4

Abstract

Low temperature device operation at 240 - 300 K temperature range is a promising approach to extend the device technology. The guideline of device design for cooling CMOS and the optimum operation temperature considering total power consumption is discussed for the first time. Also, the compatibility of cooling CMOS with advanced high-k gate dielectrics and embedded SiGe S/D technique are clarified

Keywords

CMOS integrated circuits; Ge-Si alloys; cooling; high-k dielectric thin films; low-temperature techniques; 240 to 300 K; CMOS scaling; SiGe; SiGe S/D technique; cooling CMOS; high-k gate dielectrics; low-temperature-operation technique; CMOS technology; Cooling; Degradation; Energy consumption; Germanium silicon alloys; Guidelines; High K dielectric materials; Implants; Silicon germanium; Temperature distribution;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 2006. IEDM '06. International

Conference_Location

San Francisco, CA

Print_ISBN

1-4244-0438-X

Electronic_ISBN

1-4244-0439-8

Type

conf

DOI

10.1109/IEDM.2006.346875

Filename

4154294