An automatic layout generator for I/O cells

Author

Tien, Li-Chun ; Tang, Jing-Jou ; Chang, Mi-Chang

Author_Institution

Dept. of Electron. Eng., Southern Taiwan Univ. of Technol., Tainan, Taiwan

fYear

2005

fDate

20-24 July 2005

Firstpage

295

Lastpage

300

Abstract

We present a design methodology for I/O cell library design automation. It´s different from the conventional cell library compilers or generators, which generate the cells for standard cells or regular structures (e.g., SRAM). The proposed compiler generates I/O cells based on a set of parameterized unit-cells with the features of scalable geometry dependence. The compilation results of the I/O cells have been proved in a 0.13 μm LOGIC IP8M process. Through this compiler, the number of unit-cells needed to be maintained is dramatically reduced, thereby reducing library development costs and time to market.

Keywords

circuit layout CAD; compiler generators; integrated circuit design; logic design; 0.13 micron; I/O cells; LOGIC IP8M process; automatic layout generator; cell library compiler; cell library design automation; parameterized unit-cells; scalable geometry dependence; Circuits; Consumer electronics; Design automation; Design engineering; Electric variables; Electrostatic discharge; Geometry; Libraries; Logic; Protection;

fLanguage

English

Publisher

ieee

Conference_Titel

System-on-Chip for Real-Time Applications, 2005. Proceedings. Fifth International Workshop on

Print_ISBN

0-7695-2403-6

Type

conf

DOI

10.1109/IWSOC.2005.39

Filename

1530959