Accelerating functional simulation for processor based designs

Design verification is taking an increasing proportion of the design cycle of system-on-chip (SoC) designs. Designers spend up to 70% of their time developing and running tests to verify the functionality of their systems based in 2004 IC/ASIC Functional Verification Study (2005). Running regression suites against the design can take up to several years of CPU time to complete. In this paper we show how existing software code bases can be used to reduce the time to develop and execute verification tests. These techniques can be applied to both unit and system level verification. As shown in various hardware/software co-verification tools as stated in R. Klein (1996) and M. Stanbro (1998), the overall load on a simulation can be reduced by eliminating code and data references from the set of bus cycles generated by the processor model. These same techniques can be applied by hardware designers and verification engineers to use firmware, hardware diagnostics, and other software as a basis for creating functional verification tests. This software is often available from prior versions of the design or other groups on the design team. Simulation run-times can be reduced by partitioning the processor´s memory space between the logic simulation and the processor model.