A Novel CMP-Less Integration Scheme For Dual Work Function Ni-FUSI CMOS

Author

Kubicek, S. ; De Marneffe, J-F ; Vrancken, C. ; Chiarella, T. ; Kerner, C. ; Mertens, S. ; Eyckens, B. ; Delabie, A. ; Veloso, A. ; Hoffman, T. ; Lauwers, A. ; Kittl, J.A. ; Jurczak, M. ; Biesemans, S. ; Absil, P.P.

Author_Institution

IMEC, Leuven

fYear

2006

fDate

11-13 Dec. 2006

Firstpage

1

Lastpage

4

Abstract

The authors demonstrate a novel CMP-less FUSI integration scheme which uses a spin-on sacrificial material for planarization showing 45nm gate length Ni-rich FUSI pMOS and NiSi FUSI nMOS transistors on HfSiON. This new scheme does not require CMP but remains compatible with phase-controlled dual-WF CMOS with independent silicidation of the S/D and the gate. This approach uses very selective dry etch processes that result in uniform poly-Si height, widening the RTP process window of NiSi FUSI from 5degC (Kittl et al., 2005) for the CMP approach to 15degC, without additional process complexity. Furthermore it is less disruptive compared to the standard CMP approach making it more compatible with stressed liners

Keywords

CMOS integrated circuits; MOSFET; etching; hafnium compounds; nickel compounds; planarisation; silicon compounds; work function; 15 C; 5 C; CMP-less integration; FUSI CMOS; FUSI integration; FUSI nMOS transistors; FUSI pMOS transistors; HfSiON; NiSi; RTP process window; dry etch processes; dual work function; planarization showing; spin-on sacrificial material; Dielectrics; Dry etching; Germanium silicon alloys; Instruments; MOS devices; MOSFETs; Phase control; Silicidation; Silicon germanium; Strips;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 2006. IEDM '06. International

Conference_Location

San Francisco, CA

Print_ISBN

1-4244-0439-8

Electronic_ISBN

1-4244-0439-8

Type

conf

DOI

10.1109/IEDM.2006.347006

Filename

4154441