A fast, low-power logarithm approximation with CMOS VLSI implementation

Author

SanGregory, Samuel L. ; Brothers, Charles ; Gallagher, David ; Siferd, Raymond

Author_Institution

Dept. of Electr. & Comput. Eng., Air Force Inst. of Technol., Wright-Patterson AFB, OH, USA

Volume

1

fYear

1999

fDate

1999

Firstpage

388

Abstract

A new technique and CMOS VLSI implementation for computing approximate logarithms (base 2,and 10) for binary integers is presented. The approximation is performed using only combinational logic and requires no multiplications. Additionally, as implemented, a ROM of only N×log₂(N) bits is used to convert N bit integers. The maximum error of the approximation is 1.5% when the input value is 3, and decays exponentially to less than 0.5% for input values greater than 25

Keywords

CMOS digital integrated circuits; VLSI; application specific integrated circuits; data compression; digital signal processing chips; low-power electronics; CMOS VLSI implementation; DSP chips; binary integers; combinational logic; low-power logarithm approximation; maximum error; Approximation algorithms; CMOS logic circuits; CMOS technology; Digital signal processing; Interpolation; Military computing; Read only memory; Signal processing; Signal processing algorithms; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1999. 42nd Midwest Symposium on

Conference_Location

Las Cruces, NM

Print_ISBN

0-7803-5491-5

Type

conf

DOI

10.1109/MWSCAS.1999.867287

Filename

867287