MGT: A multi-grained memory hash mechanism for embedded processor

Author

Liu, Zhenglin ; Zhu, Qingchun ; Huo, Wenjie ; Zou, Xuecheng ; Huai, Lian

Author_Institution

Dept. of Electron. Sci. & Technol., Huazhong Univ. of Sci. & Technol., Wuhan, China

fYear

2012

fDate

19-20 May 2012

Firstpage

2626

Lastpage

2632

Abstract

Memory integrity verification has been widely used to protect off-chip memory from the tamper attacks. In this paper, we propose a new hash mechanism, multi-grained hash tree (MGT), to optimize the run-time performance of memory integrity verification. This new scheme adopts variable granularities to hash the nodes on different levels, and caches these nodes in a split hash cache. The experimental results indicate that our new multi-grained scheme has 10.8% performance speedup even with a small hash cache, and reduces 53.69% initialization latency on average.

Keywords

cache storage; cryptography; embedded systems; storage management chips; trees (mathematics); MGT; embedded processor; initialization latency; memory integrity verification; multigrained hash tree; multigrained memory hash mechanism; off-chip memory protection; performance speedup; run-time performance; split hash cache; tamper attacks; Authentication; Embedded systems; Encryption; Indexes; Memory management; Vectors; Embedded Security; Hash Cache; Memory Integrity Verification; Merkle Tree; Tamper Attacks;

fLanguage

English

Publisher

ieee

Conference_Titel

Systems and Informatics (ICSAI), 2012 International Conference on

Conference_Location

Yantai

Print_ISBN

978-1-4673-0198-5

Type

conf

DOI

10.1109/ICSAI.2012.6223593

Filename

6223593